The present invention relates to a dual gate metal-semiconductor field effect transistor and a fabricating method thereof, and more particularly, to a dual gate metal-semiconductor field effect transistor which has properties of high gain and low noise by forming conductive layers with different thickness to each other at the lower part of the gate electrode by using a void structure formed by selective epitaxy on a semi-insulating GaAs substrate.
Recently, according to the rapid progress toward an information telecommunication which requires a rapidity and an accuracy, the need for ultrahigh speed computers, ultrahigh frequency communication and optical communication is more and more increasing. However, the conventional semiconductor devices based on Si have limits in satisfying these needs due to its material properties of the silicon semiconductor. Therefore, a research and development of a compound semiconductor devices using a compound semiconductor such as GaAs, Gap, Imp having a superior properties to the silicon semiconductor is being actively persued. The above compound semiconductors have superior electrical properties, such as high electron mobility and semi-insulation, so that they are advantageous for military applications and space communications owing to its lower power consumption and faster operation speed than Si. Those devices include the junction field effect transistor, the metal semiconductor field effect transistor, the heterojunction bipolar transistor and high electron mobility transistor.
The technique with relative importance is the field of MESFET in which a plurality of carriers are transferred between the metal semiconductor contacts.
Generally, the MESFET controls the current flowing through a channel formed between a source and a drain regions by varying the effective channel thickness dependent on the width of a depletion layer formed on the lower region of the gate electrode by applying a voltage to the gate electrode in Schottky contact with the region between the source and drain regions.
FIG. 1 is a cross-sectional view of the conventional dual gate MESFET.
The conventional dual gate MESFET comprises an undoped GaAs buffer layer 12 grown on the upper part of a semi-insulating GaAs substrate 10, an N-type GaAs conductive layer 13 grown on the upper part of the buffer layer 12, N-type source and drain regions 14 and 15 partially diffused to the buffer layer 12 and the conductive 13, source and drain electrodes 17 and 19 being in ohmic contacts with the source and drain regions 14 and 15, a first gate electrode 16 being in Schottky contacts with the surface of the partially recess-etched conductive layer 13 between the source and drain regions 14 and 15, and a second gate electrode 18 having a little wider width than the first gate electrode 16 and adjacent to the first gate electrode 16 on the region of the conductive layer 13 except the region which does not have recess-etching.
In such a conventional dual gate MESFET, the gain can be controlled by varying the voltage of the first gate electrode 16 or the second gate electrode 18. That is, by supplying a sufficient current to the first gate electrode 16 of MESFET of the front stage and operating the MESFET of the back stage at the maximal drain current, much electrical gain can be obtained.
The MESFET is variously applied to such a circuit processing an ultrahigh frequency signal as in mixer and automatic gain controller.
In the dual gate MESFET, the thickness h1 and h2 of the lower conductive layer 13 of the first gate electrode 16 and the second gate electrode 18 is controlled by recess-etching. The MESFET having the conducive layer 13 with different thickness by recess-etching is more stably operated in the wide band frequency region than the MESFET having the conductive layer with the same thickness of the lower part of the gate electrode. However, in this respect, a problem exists in that the process of partially recess-etching the conductive layer 13 of the lower part of the first gate electrode 16 by using a dry or wet-etching method renders the fabricating processes more complicated, such as leaving the etching remnant. Moreover, since a step difference is formed on the surface of the conductive layer 13 due to the etched region, which badly affects the following process of photolithograpy. Besides, for the purpose of preventing leakage current of the semiconductor substrate 10, the buffer layer 12 with high resistance and a good crystal condition is to be grown.